[bump process for flip chip package]

ABSTRACT

In a self-aligned method of forming a solder bump, a semiconductor die having a plurality of bumping sites is provided. Then, a plurality of solder balls is sprayed on the bumping sites of the semiconductor die. Next, the semiconductor die is vibrated to sift the solder balls positioned outside the bumping sites. Finally, by reflowing the solder balls placed on the bumping sites respectively, a plurality of solder bumps are formed on the individual bumping sites.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The Present invention relates in general to a method of forming asolder bump for Package processing. In particular, the present inventionrelates to a self-aligned method for forming a solder bump on a bumpingsite of a semiconductor die.

[0003] 2. Description of the Related Art

[0004] In conventional techniques for executing chip-to-packageinterconnections, several techniques including wire bonding and tapeautomated bonding have been utilized. However, such conventionaltechniques suffer from numerous disadvantages. For example, wire bondingis not particularly well adapted for a high density of I/O interconnectsbetween the substrate and the semiconductor die, and has an undesirablyhigh inductance due to the long electrical connection of the wires. Inaddition, wire bonding is relatively expensive, unreliable and cariesrelatively low productivity due to the demands of manual wire bonding toelectrically connect the semiconductor die and the substrate.

[0005] In an attempt to attend to deficiencies of wire bondingtechniques, so-called Controlled Collapse Chip Connection technology wasdeveloped, alternatively referred to in the art as “C4” or “flip-chip”technology. As is known in flip-chip processing, a contact is providedon an active surface of a semiconductor die in wafer form. A bumpingsite, referred to in the art as an under-bump metallization (UBM) isthen provided on the contact. Next, by using a mask with an openingcorresponding to the bumping site, Pb and Sn are co-deposited byevaporation through the opening to deposit on the individual bumpingsite. Thereafter, the semiconductor die is heated so as to reflow thePb/Sn material deposited on the bumping site to form a solder bump.After reflow, the semiconductor die is flipped and placed on a substratehaving complementary pads that align with the solder bumps. Finally,another reflow step is carried out to execute physical and electricalconnection between the die and in the substrate via the solder bumps.Nevertheless, the flip-chip technique still suffers from severaldisadvantages. For example, flip-chip technology is relatively expensivebecause it takes a long cycle time to complete and requires a mask.

[0006] In conjunction with conventional flip-chip processing, the use ofsolder balls (spheres), which places solder balls on the bumping sitesof the semiconductor die respectively, has been considered as acost-effective method to improve chip-to-package interconnectiontechnique. Please refer to FIGS. 1A and 1B, which depict a method offorming a solder bump on a semiconductor die 10 according to the priorart. As shown in FIG. 1A, a semiconductor die 10 has a plurality ofmetal pads 12, a polyimide passivation layer 14 which exposes the metalpads 12, a plurality of bumping sites 16 covered on the metal pads 12respectively, and a flux layer 18 covered on the passivation layer 14and the bumping sites 16. The bumping sites 16 in an array are composedof an adhesion layer and an UBM layer. The flux layer 18 is provided toaid in attachment of solder bumps to the bumping sites 16. A stencil 20has a plurality of stencil sites 22, a plurality of solder balls 24 heldwithin the stencil sites 22 respectively by using a vacuum from a vacuumplug chuck 26 to through holes 28 being plugged with the solder balls24. After the stencil 20 is inverted and the solder balls 24 arereleased, each solder ball 24 is placed on each bumping site 16 of thesemiconductor die 10 as shown in FIG. 1B. Since the flux layer 18provides the attachment of the solder ball 24 and the bumping site 16,the solder ball 24 becomes a solder bump for providing an electricalbridge between the semiconductor die 10 and a package substrate (notshown).

[0007] However, placing the solder balls 24 on the complementary bumpingsites by terminating the vacuum or applying an inverse-flow to purge thesolder balls 24 encounters a difficulty in accurate alignment, which maycause electrical shorts and lower reliability. Although an apparatuswith a higher level of precision in placement can solve the problem, thedrawbacks of such technique, such as relatively high expense,cost-ineffectiveness, and low productivity still exist.

SUMMARY OF THE INVENTION

[0008] An object of the present invention is to provide a self-alignedmethod of forming a solder bump on the semiconductor die.

[0009] In the method of forming a solder bump, a semiconductor diehaving a plurality of bumping sites is provided. Then, a plurality ofsolder balls is sprayed on the bumping sites of the semiconductor die.Next, the semiconductor die is vibrated to sift the solder ballspositioned outside the bumping sites. Finally, by reflowing the solderballs placed on the bumping sites respectively, a plurality of solderbumps are formed on the individual bumping sites.

[0010] It is an advantage of the present invention that the spraying andvibrating techniques can achieve the aim of self-aligned placing thesolder balls on the bumping sites. Therefore, the improved, simplifiedand controllable method for forming the self-aligned solder bump canreduce the cost. Also, the sifted solder balls can be recycled tofurther decrease production costs.

[0011] This and other objectives of the present invention will no doubtbecome obvious to those of ordinary skill in the art after having readthe following detailed description of the preferred embodiment which isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The present invention can be more fully understood by reading thesubsequent detailed description in conjunction with the examples andreferences made to the accompanying drawings, wherein:

[0013]FIGS. 1A and 1B depict a method of forming a solder bump on asemiconductor die according to the prior art.

[0014]FIG. 2 is a flow diagram showing a self-aligned method of forminga solder bump on a semiconductor die according to the present invention.

[0015]FIGS. 3A to 3D are cross-sectional diagrams showing theself-aligned method of forming a solder bump on a semiconductor dieaccording to the first embodiment of the present invention.

[0016]FIGS. 4A to 4C are cross-sectional diagrams showing theself-aligned method of forming a solder bump on a semiconductor dieaccording to the second embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT First Embodiment

[0017] Please refer to FIGS. 2 and 3A to 3D. FIG. 2 is a flow diagram ofa self-aligned method of forming a solder bump 46 on a semiconductor die30 according to the present invention. FIGS. 3A to 3D arecross-sectional diagrams of the self-aligned method of forming a solderbump 46 on a semiconductor die 30 according to the first embodiment ofthe present invention. In the first embodiment, the self-aligned methodin applied to small solder balls. First, a plurality of solder balls 42,preferably about 1˜10microns in diameter, are provided as indicated instep 100. Depending on the substrate materials and the thermal historyof the semiconductor device, any known compositions for the solder balls42 may be utilized, such as high lead solder (Pb/Sn) or eutectic solder.Then, the solder balls are inspected for uniformity so as to identifynon-uniform solder balls, such an balls having a defect or non-sphericalshape beyond a certain tolerance.

[0018] Then, as shown in FIG. 3A, step 200 provides a semiconductor die30 having a semiconductor substrate 32, a plurality of metal pads 34formed on the semiconductor substrate 32, a polyimide passivation layer36 which has a plurality of openings 38 for exposing the metal pads 34,and a plurality of bumping sites 40 formed at least on the sidewall andbottom of the openings 38 to cover the exposed metal pads 34respectively. Each of the bumping sites 40 is composed of a Cr adhesionlayer and a UBM layer made up of one or multiple layers. In thesemiconductor substrate 32, various conducting and insulating layers aretypically grown, deposited, and etched to form integrated circuitry.

[0019] Turning to FIG. 3B, step 300 provides a plurality of solder balls42 on the surface of the semiconductor die 30 by spraying the solderballs 42 from a nozzle 44. Most of the solder balls 42 drop to thebumping sites 40 so as to fill the openings 38, and a few of the solderballs 42 fall on the surface of the passivation layer 36. Next, as shownin FIG. 3C, step 400 provides a vibrating technique, such as anultrasonic vibration, to sieve out the solder balls 42 that droppedoutside the bumping sites 40, and rearrange the solder balls 42 droppedinto the openings 38 for limiting the vacant space. Consequently, thesolder balls 42 are self-aligned placed on the individual bumping site40. It is noted that the solder balls 42 that are sieved out can bereserved in a tank and recycled.

[0020] Finally, as shown in FIG. 3D, step 500 provides a temperaturereaching the melting point of the solder balls 42 to reflow the solderballs 42 placed on the bumping site 40 by any heating method, such as anIR lamp or a hot plate. As a result, on the individual bumping site 40,the solder balls 42 are melted into a solder bump 46 with a curved face,protruding from the passivation layer 36. While a single semiconductordie 30 is bumped as shown in FIGS. 3A to 3D with respect the firstembodiment of the present invention, it is to be understood that aplurality of semiconductor dies, still in wafer form, may be bumped atthe same time.

[0021] Thereafter, the bumped semiconductor die 30 may be attached to aceramic substrate or a plastic substrate by flip-chip ball grid array(BGA) technique. The application field of the bumped semiconductor die30 comprises semiconductor products, liquid crystal displays, andcommunication circuit.

[0022] Compared with the prior bumping method, in the self-alignedmethod of forming the solder bump 46, spraying and vibrating techniquesthat substitute the scientific apparatus with a higher level ofprecision in placement can achieve the aim of self-aligned placing thesolder balls on the bumping site. It is clear that according to thepresent invention, an improved, simplified and controllable method forforming a self-aligned solder bump 46 can reduce the cost. Also, thesifted solder balls 42 can be recycled for further decreasing theproduction cost.

Second Embodiment

[0023] Please refer to FIGS. 4A to 4C, which are cross-sectionaldiagrams of the self-aligned method of forming a solder bump 46 on asemiconductor die 30 according to the second embodiment of the presentinvention. In the second embodiment, the self-aligned method is appliedto solder balls of relatively larger sizes ranging from 100 to 500microns. First, a plurality of such relatively larger solder balls 48areprovided as indicated in step 100. Depending on the substrate materialsand the thermal history of the semiconductor device, any knowncompositions for the solder balls may be utilized, such as high leadsolder (Pb/Sn) or eutectic solder. Then, the solder balls are inspectedfor uniformity so as to identify non-uniform solder balls, such as ballshaving a defect or non-spherical shape beyond a certain tolerance.

[0024] Then, step 200 provides the above-mentioned semiconductor die 30having the semiconductor substrate 32, the metal pads 34, the polyimidepassivation layer 36 that has openings 38 for exposing the metal pads34, and the bumping sites 40. Next, as shown in FIG. 4A, step 300 spraysthe solder balls 48 on the surface of the semiconductor die 30 with anyspraying apparatus. Since the diameter of the solder ball 48 is almostequal to the width of the opening 38, only one solder ball 48 can fitinto the individual bumping site 40, and the rest of the solder balls 48may fall on the surface of the passivation layer 36. Next, as shown inFIG. 4B, step 400 provides a vibrating technique, such as an ultrasonicvibration, to sieve out the big solder balls 48 that are dropped outsidethe bumping sites 40, and thereby each of the big solder balls 48 fitinto the individual bumping site 40 in a self-aligned manner. It isnoted that the big solder balls 48 that are sieved out can be reservedin a tank and recycled.

[0025] Finally, as shown in FIG. 4D, step 500 provides a temperaturereaching the melting point of the big solder balls 48 to reflow the bigsolder balls 48 on the individual bumping site 40 by any heating method,such as an IR lamp or a hot plate. As a result, on each of the bumpingsites 40, the solder ball 48 is melted into a solder bump 46 with acurved face, protruding from the passivation layer. While a singlesemiconductor die is bumped as shown in FIGS. 4A to 4C with respect tothe second embodiment of the present invention, it is to be understoodthat a plurality of semiconductor dies, still in wafer form, maybebumped at the same time.

[0026] Those skilled in the art will readily observe that numerousmodifications and alterations of the device may be made while retainingthe teaching of the invention. Accordingly, the above disclosure shouldbe construed as limited only by the metes and bounds of the appendedclaims.

What is claimed is:
 1. A method of forming a solder bump, comprising thesteps providing a semiconductor die having a plurality of bumping sites;spraying a plurality of solder balls on the plurality of bumping sitesof the semiconductor die; sifting the solder balls positioned outsidethe plurality of bumping sites by vibrating the semiconductor die; andforming a plurality of solder bumps by reflowing the solder ballspositioned on the plurality of bumping sites.
 2. The method as claimedin claim 1, wherein the sifting step retains one solder ball on each ofthe bumping sites.
 3. The method as claimed in claim 2, wherein thesolder balls are about 100˜500 microns in diameter.
 4. The method asclaimed in claim 1, wherein the sitting step retains a plurality ofsolder balls on each of the bumping sites.
 5. The method as claimed inclaim 4, wherein the solder balls are about 1˜10microns in diameter. 6.The method as claimed in claim 1, wherein the semiconductor diecomprises: a plurality of metal pads; a passivation layer covered on thesemiconductor die and having a plurality of openings for exposing theplurality of metal pads respectively; an under-bump metallization (UBM)layer covered on the bottom and sidewall of the openings; and anadhesion layer on the UBM layer; wherein the UBM layer and the adhesionlayer provide the bumping sites in array.
 7. The method a claimed inclaim 1, wherein the sifting step employs an ultrasonic vibrationtechnique to sift the solder balls positioned outside the bumping sites.8. The method as claimed in claim 1, wherein the reflowing step providesa temperature reaching the melting point of the solder balls.
 9. Themethod as claimed in claim 1, wherein the reflowing step employs an IRlamp.
 10. The method as claimed in claim 1, wherein the reflowing stepemploys a hot plate.
 11. The method as claimed in claim 1, wherein thesemiconductor die is in wafer form.